It is often desirable to generate internal voltages which are higher than the available power supply voltage for certain integrated circuit applications. For example, an operating voltage of 10V to 12V is usually required for programming a nonvolatile memory cell, such as an EPROM or a Flash memory. To meet this demand, charge pumping circuits are typically used to generate such on-chip high voltages. The conventional voltage multiplier circuit proposed by J. F. Dickson in IEEE Journal of Solid-State Circuits, vol. SC-11, pages 374-378, June 1976, is shown in FIG. 1. The original circuit consists of many diodes and capacitors. Capacitors C and Cs are the pumping capacitors and the stray (parasitic) capacitors, respectively. The circuit is also driven by two nonoverlapping clocks, .o slashed.1 and .o slashed.2. The clock amplitude V.sub..o slashed. is usually the same as the power supply voltage VDD. The output voltage of the circuit, Vout, can be expressed as ##EQU1## where Vd is the forward voltage drop of a diode, n is the number of pumping stages, Iout is the output current loading and f is the frequency of the driving clock.
From the above equation, it is clear that the magnitude of the output voltage Vout has a proportional relationship to the number of pumping stages and to the clock amplitude V.sub..o slashed.. Although this conventional charge pumping circuit may be used for on-chip high voltage generation, its stability is sensitive to process variations and operating conditions, such as temperature and voltage.
To enhance the reliability of nonvolatile memory, a constant voltage generating circuit is often desired. For this purpose, modifications to the Dickson voltage multiplier circuit have been developed in the prior art.
One example is disclosed in Japanese Patent Application Laid-open Publication JP-A-4-372571, as shown in FIG. 2. This constant voltage generating circuit comprises a step-up circuit 50 (charge pumping circuit), a clamp circuit 60a, a voltage detecting circuit 70a, and a clock control circuit 80a. (For detailed circuit descriptions, please refer to U.S. Pat. No. 5,499,183, Column 1, line 12, to Column 2, line 46, in regard to FIG. 1A). In summary, the output voltage VPP is initially `logic low`. As its voltage level is stepped up, the voltage level VB is elevated to `logic high`. The output of inverter I71 changes its state to `logic low`, so that the external clock is disabled by NAND gate N81. Since the external clock is not transmitted to the clock input terminal, the step-up circuit 50 stops its operation. Once the step-up circuit 50 stops its operation, the output voltage VPP is maintained at a constant voltage level, with reduced power dissipation. However, the clamp circuit 60a is basically a resistive voltage divider, so this circuit has a certain level of dc power consumption. In addition, the voltage detecting circuit, inverter I71, has a logic threshold voltage which is inherently sensitive to process variation and operating voltage. Therefore, it is difficult to obtain a precise, stable VPP voltage.
Another example is disclosed in U.S. Pat. No. 5,602,794, issued to J. J. Javanifard et al. This invention relates to a charge pump with a variable number of stages, as opposed to a fixed number of stages. As shown in FIG. 3, the two charge pumping circuits 110 and 120 are connected in parallel for the lower voltage generation, while for the higher voltage generation, the two charge pumping circuits are connected in series, via control switches 130 and 131. Therefore, the output voltage level can be controlled by changing the interconnecting configuration of charge pumping circuits.
A similar prior art technique is disclosed in U.S. Pat. No. 5,574,634, issued to D. B. Parlour et al. As shown in FIG. 4, a voltage tripler circuit has a comparator U51 to detect the output voltage from the capacitive voltage divider (capacitors C51 and C52). Initially, the voltage level at node N53 is `logic low`, such that the output of comparator U51 is `logic high`, and the output Q of latch L51 is also `logic high`. Therefore, all pumping capacitors C54 and C55 are activated by nonoverlapping clock signals .o slashed.1 and .o slashed.2. When VPP is high enough, the output of the comparator U51 changes its state to `logic low`. As a result, the output Q of latch L51 is also `logic low`, which disables the pumping operation of capacitor C54. Once the pumping capacitor C54 stops its operation, the output VPP is maintained at its voltage level by the pumping capacitor C55. With regard to minimizing dc power consumption, the capacitive voltage divider of Parlour et al. is preferable to the prior art resistive voltage divider of FIG. 2. However, the circuit shown in FIG. 4 still focuses on controlling the output voltage by varying the number of pumping stages, which makes it difficult to achieve a precise, stable output voltage level.
Accordingly, it is an object of the present invention to overcome the disadvantages of the prior art. It is a further object of the present invention to minimize dc power consumption in the inventive circuit.